An iterative combinational logic synthesis technique using spectral information

Iterative Combinational Logic Synthesis Techniques Using Spectral Data

Iterative Combinational Logic Synthesis Techniques Using Spectral Data

The hierarchical timing pair model

We present a new model for representing timing information for functions in High-Level Synthesis (HLS). We identify shortcomings of the conventional timing model, which is a very simple model derived from the combinational logic model, and show that our new model overcomes many of these defects. In particular, we are able to provide a unified timing model that describes hierarchical combination...

Fuzzified Simulated Evolution Algorithm for Combinational Digital Logic Design Targeting Multi-objective Optimization

In this paper, we employ fuzzified Simulated Evolution (SimE) algorithm for combinational digital logic design targeting area, delay and power as objectives. This technique is considered to be an evolutionary technique in logic design compared to conventional technique which uses deterministic algorithms for logic design. The performance of the proposed algorithm is evaluated using selected ISC...

Self-Timed Realization of Combinational Logic

A novel synthesis method for self-timed realization of arbitrary combinational logic functions is presented in this paper. The cost of self-timed implementation of a large number of conventional combinatorial benchmarks is provided. A new self-timed system configuration is also proposed in support of the synthesis heuristic that generally favors weakly indicating realizations of combinational l...